1. Field of the Invention
This invention relates to structure for a MIS device, and in particular, to a structure for preventing an unwanted inversion layer of a field portion (other than an active region of the MIS device).
2. Description of the Prior Art
When a plurality of MIS FETs are formed in a single semiconductor substrate, they are electrically connected to each other through a metallic interconnection layer overlying a protective layer formed on one fce of the substrate. And when a voltage is applied to the metallic interconnection layer, an electric field from the metallic interconnection layer builds up an electric charge in an interface region between the semiconductor substrate and the protective layer. Because of this, unwanted parasitic conduction paths are induced in the surface region of the semiconductor substrate. If the unwanted parasitic conduction paths are induced between active regions of the MIS FETs, the active regions are short-circuited.
In one conventional method for preventing the unwanted parasitic conduction paths, the thickness of the protective layer over the field portion is increased. The unwanted parasitic conduction paths or the inversion paths can be avoided by this method, but it is difficult to manufacture a thick protective layer without trouble. For example, edge portions of the metallic interconnection layer over the thick protective layer are apt to break.
In another conventional method for suppressing the spread of the unwanted inversion paths, a special region, called a channel stopper region, is formed in the semiconductor substrate. Such a method will be described in detail with reference to a C/MOS inverter circuit as shown in FIG. 1 and FIG. 2. In referring to FIG. 2, note that it is taken along a section line going from the left hand edge to the electrode 11, then downwardly and finally back to the left hand edge again.
A P-type semiconductive region 2 is formed in the left half (FIG. 2) of an N-type silicon semiconductor substrate 1. N-type semiconductive regions 3 and 4 as a source region and a drain region are formed in the P-type semiconductive region 2. A P-type semiconductive region 5 as a channel stopper region is formed around the P-type semiconductive region 2, so as to surround the N-type semiconductive regions 3 and 4. P-type semiconductive regions 6 and 7 as a source region and a drain region are formed in the right half (FIG. 2) of the N-type semiconductor substrate 1. An N-type semiconductive region 8 as a channel stopper region is formed around the P-type semiconductive regions 6 and 7. A SiO.sub.2 layer 9 is formed on the semiconductor substrate 1 and openings are made therein which are filled with electrodes 10, 12 and 13, respectively. Moreover, a recess is made in the SiO.sub.2 layer 9. This recess is filled with an electrode 11. One MIS-FET comprises the electrode 11, the P-type semiconductive region 2 and the SiO.sub.2 layer 9 interposed between the electrode 11 and the P-type semiconductive region 2. Another MIS-FET comprises the electrode 11, the N-type semiconductor substrate 1 and the SiO.sub.2 layer 9 interposed between the electrode 11 and the N-type semiconductor substrate 1. An input voltage V.sub.IN is applied to the electrode 11. An output voltage V.sub.OUT is obtained from the electrode 12 which extends between the N-type semiconductive region 4 and the P-type semiconductive region 6. Thus, a complementary C/MOS inverter is constituted by the two MIS FETs.
The surface regions of the semiconductor substate 1 except the active regions, namely, the N-type semiconductive regions 3 and 4, the P-type semiconductive regions 6 and 7 and the portions lying right under the electrode 11 are called "field portions" or "parasitic portions". MOS-structures are formed at the field portions. According to the low frequency measurement of the C-V characteristics of the MOS-structure, the capacitance changes with the increase of the absolute value of the applied negative voltage, as shown in FIG. 3. The capacitance rapidly rises at the voltage V.sub.1. It is known from the fact that an inversion layer is formed in the field portion.
When a high voltage is applied to the electrode, the inversion layer is formed in the surface region of the semiconductor substrate. Accordingly, a channel is formed between the two MOS-FETs due to the inversion layer. When the MOS-FETs are operated at a high speed, a high voltage is applied to the MOS-FETs. In such a case, a higher threshold voltage V.sub.TH is required for the field portion. For that purpose, it is necessary to arrange the P-type semiconductive region 5 and the N-type semiconductive region 8 as channel stopper regions, or to thicken the SiO.sub.2 layer 9. Generally, the impurity concentration is 10.sup.14-10.sup.15 atoms/cm.sup.3 in the semiconductor substrate 1, while it is 10.sup.15-10.sup.16 atoms/cm.sup.3 in the surface region of the P-type semiconductive region 2. When a &lt;100&gt; oriented silicon is used in the above-mentioned condition of the impurity concentrations, the threshold voltage .vertline.V.sub.TH .vertline. for the field portion is as little as about 10V at the thickness 1 micron of the SiO.sub.2 layer 9.
However, when the channel stopper regions are arranged in the semiconductor substrate without widening the surface area of the semiconductor substrate, they contact with the drain region, so that the breakdown voltage of the drain region is lowered. Since it is undesirable to lower the breakdown voltage of the drain region, the drain region and the channel stopper regions should be spaced from each other by over several microns. Accordingly, the surface area of the semiconductor becomes wider. This is very disadvantageous.
When a SiO.sub.2 layer as an insulating layer is formed on the field portion, the conventional MOS-FET is not stable against sodium ions (Na.sup.+ ) in bias temperature stress between the electrode and the semiconductor substrate. The threshold voltage V.sub.TH for the field portion varies. This creates a problem as to reliability in the conventional MOS-FET.